Semiconductor wafers are generally prepared from a single crystal ingot (e.g., a silicon ingot) which is then sliced into individual wafers. In some applications, a multi-layered structure (sometimes generically referred to as a multi-layered structure or simply as a wafer) may be used. A common form of multi-layered structure is a semiconductor on insulator structure, one of the most common of which is a silicon-on-insulator (SOI) wafer. An SOI wafer typically includes a thin layer of silicon atop a dielectric layer (i.e., an insulating layer) which is in turn disposed on a substrate (i.e., a handle wafer). Typically the substrate or handle wafer is silicon.
An example process of making an SOI wafer includes depositing a layer of oxide on a polished front surface of a donor wafer. Particles (e.g., hydrogen atoms or a combination of hydrogen and helium atoms) are implanted at a specified depth beneath the front surface of the donor wafer. The implanted particles form a cleave plane in the donor wafer at the specified depth at which they were implanted. The surface of the donor wafer may be cleaned to remove organic compounds deposited on the wafer during the implantation process.
The front surface of the donor wafer is then bonded to a handle wafer to form a bonded wafer through a hydrophilic bonding process. In some processes, the donor wafer and the handle wafer are bonded together by exposing the surfaces of the wafers to a plasma containing, for example, oxygen or nitrogen. Exposure to the plasma modifies the structure of the surfaces in a process often referred to as surface activation. The wafers are then pressed together and a bond is formed therebetween. The donor wafer is thereafter separated (i.e., cleaved) along the cleave plane from the bonded wafer to form the SOI wafer.
The resulting SOI wafer comprises a thin layer of silicon (the portion of the donor wafer remaining after cleaving) disposed atop the oxide layer and the handle wafer. The cleaved surface of the thin layer of silicon has a rough surface that is ill-suited for end-use applications. The damage to the surface may be the result of the particle implantation and the resultant dislocations in the crystal structure of the silicon. Accordingly, additional processing is required to smooth the cleaved surface.
Known methods used to smooth and thin the surface layer of silicon (i.e., the cleaved surface) include combinations of annealing, chemical-mechanical polishing, high-temperature gaseous etching (i.e., epitaxial smoothing or “epi-smoothing”), and the formation of a sacrificial oxide layer on the cleaved surface. These smoothing processes are generally carried out using the same process parameters for each SOI wafers. That is, the processing conditions for current smoothing processes are generally not adjusted between SOI wafers within the same batch.
Current fabrication processes for SOI wafers have provided satisfactory thickness uniformity in the top silicon layer for most applications. However, current smoothing processes provide less than optimal thickness uniformities for certain applications, such as extremely thin SOI (ETSOI) applications or applications requiring fully depleted transistor gates, because the thickness uniformity requirements for such applications are sometimes more stringent. For example, industry specifications for partially depleted SOI (PDSOI) applications permit a top layer thickness uniformity of 30 angstroms (Å) or more, while fully depleted SOI (FDSOI) applications require a top layer thickness uniformity of 10 Å or less. Accordingly, a need exists for an SOI wafer processing system and method that enables the production of SOI wafers with silicon layers having improved thickness uniformity.
This Background section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.